The present invention relates to a static type semiconductor memory and, more particularly, to sense circuit technology which is suitable for achieving a high speed operation and a low power consumption.
The sense circuits of conventional static type semiconductor memories are discussed in ISSCC86,Digest of Technical Papers (1986), pp.208-209, and IEEE, Journal of Solid State Circuits, SC-21 (1986), pp.692-703.
The present inventors set the development target of our static type semiconductor memory to a large memory capacity, i.e., 1 megabits or more, a high speed, i.e., an access time of 40 nanoseconds or less, and a low power consumption, i.e., an operating power consumption of 0.5 watt or less.
In the above-mentioned prior art which have no substantial consideration is given to achievement of a high speed operation and a low power consumption, which are part of our development target.
FIG. 3 shows a static type memory studied by the present inventors prior to the filing of this application. In the figure, the reference numeral 1 denotes a memory cell, 2 a word line, 3 a column switch for selectively connecting predetermined data line pair 4 to first data bus line pair 5, an initial stage sense amplifier 7, a post-stage sense amplifier 8, 5'second data bus line pair for transmitting a pair of the outputs of the postage sense amplifier 8 to a main amplifier 11, an output buffer 12, 18 a signal output terminal 18, a data latch circuit 20 incorporated in the output buffer 12, and an equalizing circuit 10.
In the memory shown in FIG. 3, the outputs of the sense amplifiers 7 and 8 are directly connected to the second data bus lines pair 5'. Therefore, the sense amplifier operation is enabled during only the initial period of the operation cycle, and the amplified signal must be latched in the latch circuit 20 within the output buffer 12. In this case, in order to avoid latching of error information attributable to offset of the amplifiers 7, 8 and 11, a sufficient time margin is needed for latching, which is unsuitable for achieving a high speed operation.
The studies conducted have also revealed that no consideration is given to equalization of complementary signals at the stages which are subsequent to the sense amplifier 7, but equalization of these complementary signals are successively effected as far as the output line pair of the main amplifier 11 on the basis of the equalization effected between the complementary input signal line pair of the initial stage, sense amplifier 7 by the equalizing circuit 10. Therefore, a long time is required to complete the equalization necessary for the entire system, which is also unsuitable for achieving a high speed operation.